Updated 2015-09-17 22:01:04 by Ethouris

The 'tcmake' name was created especially for publishing :) - normally it's referred to as "make.tcl".

This tool is currently part of a bigger project named Silvercat, please the Wiki page with description here: https://gitlab.com/silvercat/silvercat/wikis/Tclmake

This script doesn't do anything magic, just replays the standard POSIX make tool with Tcl syntax.

The makefile's syntax is almost the same simple as the syntax of the make's makefile. It supports also some symbols and automatic variables as the make tool.

The make.tcl script can be called with one target name, which is the first found rule by default. First it searches for the makefile, which must be named "Makefile.tcl" or "makefile.tcl". This must be a tcl script, which is sourced by make.tcl.

The Makefile.tcl is a normal Tcl script and you can program anything there, however the most important is creating rules. This can be done by use of two commands: rule and rules.

The rule command has the following syntax:
 rule <target> <dependency>... <action>

After <target> there can be any number of dependencies and the last argument is the action. A typical structure of the "rule" command is:
 rule f1.o f1.c f.h {
    gcc -c f1.c

Additionally, there's also a [phony] command, which either defines a new target WITHOUT a command (only dependencies), or sets the already defined target (by "rule" command) as phony.

Commands in action can be either shell commands or special commands, if start with '!'. These commands are:

  • !tcl <script> - execute a Tcl command
  • !link <target> - execute action defined for <target>

To define an action for multiple targets you can use 'rules' command:
 rules <rule list> <action>

Typical use is:
 rules {
    {f1.o f1.c f.h}
    {f2.o f2.c f.h}
 } {
    gcc -c $<

Additionally, you can use any command defined in the make.tcl in your Makefile.tcl. For example:

  • make - perform make action for target
  • depends - prints on stdout all defined dependencies, in makefile form

And, of course, if you end your Makefile.tcl with 'exit' command, no normal action will be taken... :)

  -f another-name-of-makefile
  -k (keep going, even if some of command execution resulted in error)
  -v (be verbose)
  -d (be very, very talkative)

Happy making :)


see also:

software build systems in Tcl, ynform.org